high-performance 4mb synchronous cmos sram copyright ?2000 alliance semiconductor. all rights reserved. ? as7c3128pfs32/36a 6/8/00 alliance semiconductor 1 128k 32/36 synchronous sram features ? organization: 131,072 words 32 or 36 bits ? fast clock speeds to 166 mhz in lvttl/lvcmos ? fast clock to data access: 3.5/3.8/4/5 ns ?fast oe access time: 3.5/3.5/3.8/4 ns ? fully synchronous register-to-register operation ? single register flow-through mode ? single cycle de-select ? pentium? compatible architecture and timing ? synchronous and asynchronous output enable control ? economical 100-pin tqfp package ? byte write enables ? clock enable for operation hold ? multiple chip enables for easy expansion ? 3.3 core power supply ? 2.5v or 3.3v i/o operation with separate v ddq ? automatic power down: 10 mw typical standby power ? ntd? pipeline architecture available (as7c3128kntd32/36) logic block diagram q0 q1 128k32/36 memory array burst logic clk clr ce address dq ce clk dqd clk dq byte write registers register dqc clk dq byte write registers dqb clk dq byte write registers dqa clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down data [35:0] 36 4 36 36 17 15 17 17 gwe bwe bw d adv adsc adsp clk ce0 ce1 ce2 bw c bw b bw a oe a[16:0] zz lbo oe le ft clk clk pin arrangement dqpc/nc dqc dqc v ddq v ssq dqc dqc dqc dqc v ssq v ddq dqc dqc ft v dd v dd v ss dqd dqd v ddq v ssq dqd dqd dqd dqd v ssq v ddq dqd dqd dqpd/nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqpb/nc dqb dqb v ddq v ssq dqb dqb dqb dqb v ssq v ddq dqb dqb v ss zz dqa dqa v ddq v ssq dqa dqa dqa dqa v ssq v ddq dqa dqa dqpa/nc lbo a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc nc a10 a11 a12 a13 a14 a15 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a6 a7 ce0 ce1 bwd bwc bwb bwa ce2 v dd v ss clk gwe bwe oe adsc adsp adv a8 a9 tqfp 14x20mm v dd v dd a16 note: pins 1,30,51,80 are nc for 32 selection guide as7c3128pfs32/36a 3.5 as7c3128pfs32/36a -3.8 as7c3128pfs32/36a -4 as7c3128pfs32/36a -5 units minimum cycle time 6 6.7 7.5 10 ns maximum clock frequency 166.7 150 133.3 100 mhz maximum pipelined clock access time 3.5 3.8 4 5 ns maximum operating current 350 325 300 250 ma maximum standby current 60 60 60 60 ma maximum cmos standby current (dc) 5555ma advance information
? 2 alliance semiconductor 6/8/00 as7c3128pfs32/36a functional description the as7c37c3128pfs32/36a family is a high performance cmos 4 mbit synchronous static random access memory (sram) organized as 131,072 words 32 or 36 bits and incorporates a two stage register-register pipeline for highest frequency on any given technology. timing for this device is compatible with existing pentium synchronous cache specifications. this architecture is suited for asic, dsp (tms320c6x), and powerpc based systems in computing, datacomm, instrumentation, and telecommunications systems. when using pipeline burst srams, any turnaround from read-to-write and write-to-read, required the insertion of two dead cycles. when reading data, a two cycle latency until data valid exists due to the nature of the dual register architecture. when writing, data, address and controls are all presented simultaneously. therefore two dead cycles are required to clear the read pipeline before a write can occur. in a write-to-read transition, two dead cycles are again produced due to t he pipeline read latency. these penalties are eliminated in the as7c3128kntd32/36 architecture device. fast cycle times of 6/6.7/7.5/10 ns with clock access times (t cd ) of 3.5/3.5/3.8/4 ns enable 167, 150, 133 and 100 mhz bus frequencies. three chip enable inputs permit easy memory expansion. burst operation is initiated in one of two ways: the controller address strobe ( adsc ), or the processor address strobe ( adsp ). the burst advance pin ( adv ) allows subsequent internally generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address clocked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation the data accessed by the current address, registered in the address registers by the positive edge of clk, are carried to the data-out registers and driven on the output pins on the next positive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when we is sampled high, adv is sampled low, and both address strobes are high. burst operation is selectable with the mode input. with mode unconnected or driven high, burst operations use a pentium count sequence. with mode driven low the device uses a linear count sequence, suitable for powerpc and many other applications. write cycles are performed by disabling the output buffers with oe and asserting a write command. a global write enable gwe writes all 32 bits regardless of the state of individual bw[a:d] inputs. alternately, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bw signal(s). bwn is ignored on the clock edge that samples adsp low, but is sampled on all subsequent clock edges. output buffers are disabled when bwn is sampled low (regardless of oe ). data is clocked into the data input register when bwn is sampled low. address is incremented internally to the next burst of address if bwn and adv are sampled low. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp follow. ?adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . ?we signals are sampled on the clock edge that samples adsc low (and adsp high). ? master chip select ce0 blocks adsp , but not adsc . the as7c3128k36p family operates from a 3.3v supply. i/os use a separate power supply that can operate at 2.5v or 3.3v. this device is available in a 100-pin 1420 mm tqfp package. capacitance 1 write enable truth table (per byte) key: x = dont care, l = low, h = high. ? va li d rea d . parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 5 pf i/o capacitance c i/o i/o pins v in = v out = 0v 7 pf gwe bwe bwn write n lxxt xl l t hhxf hl hf ?
? as7c3128pfs32/36a 6/8/00 alliance semiconductor 3 signal descriptions absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute max- imum rating conditions may affect reliability. signal i/o properties description clk i clock clock. all inputs except oe are synchronous to this clock. a0Ca16 i sync address. sampled when all chip enables are active and adsc or adsp are asserted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 isync master chip enable. sampled on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the synchronous truth table for more information. ce1, ce2 isync synchronous chip enables. active high and active low, respectively. sampled on clock edges when adsc is active or when ce1 and adsp are active. adsp i sync address strobe processor. asserted low to load a new bus address or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new address or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe i sync default = high global write enable. asserted low to write all 36 bits. when high, bwe and we0 Cwe3 control write enable. this signal is internally pulled high. bwe i sync default = low byte write enable. asserted low with gwe = high to enable effect of we0 Cwe3 inputs. this signal is internally pulled low. bw[a,b,c,d] isync write enables. used to control write of individual bytes when gwe = high and bwe = low. if any of bw[a:d] is active with gwe = high and bwe = low the cycle is a write cycle. if all bw[a:d] are inactive the cycle is a read cycle. oe iasync asynchronous output enable. i/o pins are driven when oe is active and the chip is synchronously enabled. lbo i static default = high count mode. when driven high, count sequence follows intel xor convention. when driven low, count sequence follows linear convention. this signal is internally pulled high. 18 ft istatic flow-through mode.when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. zz i async sleep. places device in low power mode; data is retained. connect to gnd if unused. parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq C0.5 +4.6 v input voltage relative to gnd (input pins) v in C0.5 +4.6 v input voltage relative to gnd (i/o pins) v in C0.5 v ddq + 0.5 v power dissipation p d C1.2w dc output current i out C30ma storage temperature (plastic) t stg C65 +150 o c temperature under bias t bias C65 +135 o c
? 4 alliance semiconductor 6/8/00 as7c3128pfs32/36a synchronous truth table key: x = dont care, l = low, h = high. ? see write enable truth table for more information. recommended operating conditions dc electrical characteristics over operating range ce0 ce1 ce2 adsp adsc adv write n ? oe address accessed clk operation h x x x l x x x na l to h deselect l l xl xxx xna l to hdeselect l l xhl xx xna l to hdeselect l xhl xxx xna l to hdeselect lxhhlxx xna l to hdeselect lhllxxf lexternal l to hbegin read lhllxxf hexternal l to hbegin read lhlhlxf lexternal l to hbegin read lhlhlxf hexternal l to hbegin read xxxhhl f l next l to hcont. read xxxhhl f hnext l to hcont. read xxxhhhf l current l to hsuspend read xxxhhhf hcurrent l to hsuspend read hxxxhl f l next l to hcont. read hxxxhl f hnext l to hcont. read h x x x h h f l current l to h suspend read h x x x h h f h current l to h suspend read lhlhlxt xexternal l to hbegin write xxxhhl t xnext l to hcont. write hxxxhl t xnext l to hcont. write xxxhhht hcurrent l to hsuspend write h x x x h h t h current l to h suspend write parameter symbol min nominal max unit supply voltage v dd 3.135 3.3 3.6 v gnd 0.0 0.0 0.0 v i/o supply voltage v ddq 2.35 2.5 or 3.3 3.6 v gnd q 0.00.00.0v input voltages address and control pins v ih 2.0C 4.5v v il C0.5 * * v il min = C2.0v for pulse width less than 0.2 x t rc . C0.8v i/o pins v ih 2.0 C v ddq + 0.5 v v il -0.5 * C0.8 ambient operating temperature t a 0C70c parameter symbol test conditions -166-150-133-100 unit min max min max min max min max input leakage current | i li | v dd = max, v in = gnd to v dd C2C2C2C2a output leakage current | i lo | oe 3 v ih, v dd = max, v out = gnd to v dd C2C2C2C2a
? as7c3128pfs32/36a 6/8/00 alliance semiconductor 5 timing characteristics over operating range see notes on page 9. key to switching waveforms operating power supply current i cc ce = v il , ce = v ih , ce = v il , f = f max, i out = 0 ma C 350 C 325 C 300 C 250 ma standby power supply current i sb deselected, f = f max C60C60C60C60ma i sb1 deselected, f = 0 , all v in 0.2v or 3 v dd - 0.2v C5C5C5C5ma output voltage v ol i ol = 8 ma, v ddq = 3.6v C 0.4 C 0.4 C 0.4 C 0.4 v v oh i oh = C8 ma, v ddq = 3.0v 2.4 C 2.4 C 2.4 C 2.4 C v parameter symbol -3.5 -3.8 -4 -5 unit notes minmaxminmaxminmaxminmax clock frequency f max -166-150-133-100mhz1 cycle time (pipelined mode) t cyc 6 -6.6-7.5- 10- ns clock access time (pipelined mode) t cd -3.5-3.8-4-5ns clock access time (flow-through mode) t cdf - 6 - 6.6 - 7.5 - 10 ns output enable low to data valid t oe -3.5-3.5-3.8- 4 ns clock high to output low z t lzc 0-0-0-0-ns8 data output hold from clock high t oh 1.5-1.5-1.5- 2 - ns8 output enable low to output low z t lzoe 1-1-1.5-2-ns8 output enable high to output high z t hzoe -3-3.5-4-4ns8 clock high to output high z t hzc -2.5- 3 -3.5-3.5ns8 clock high to output high z t hzcn -1.5-1.5- 2 -2.5ns1,9 clock high pulse width t ch 2.4-2.6-2.8- 3 - ns clock low pulse width t cl 2.4-2.6-2.8- 3 - ns address and control setup to clock high t as 1 -1.3-1.5-1.5- ns data setup to clock high t ds 1 -1.3-1.5-1.5- ns write setup to clock high t ws 1 -1.3-1.5-1.5- ns chip select setup to clock high t css 1 -1.3-1.5-1.5- ns address hold from clock high t ah 0.5-0.5-0.5-0.5- ns data hold from clock high t dh 0.5-0.5-0.5-0.5- ns write hold from clock high t wh 0.5-0.5-0.5-0.5- ns chip select hold from clock high t csh 0.5-0.5-0.5-0.5- ns output rise time (0 pf load) t r 1.5-1.5-1.5-1.5-v/ns1 output fall time (0 pf load) t f 1.5-1.5-1.5-1.5-v/ns1 parameter symbol test conditions -166 -150 -133 -100 unit min max min max min max min max undefined/don?t care falling input rising input
? 6 alliance semiconductor 6/8/00 as7c3128pfs32/36a timing waveform of read cycle note: ? = xor when mode = high/no connect; ? = add when mode = low. refer to burst sequence table. we [0:3] is dont care. t cyc t ch t cl t ss t sh t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe d out t css t csh t hzc t lzoe t cd t lzc t oe t wh t advh t hzoe t ss t sh load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a3y11) q(a1) a2 a1 a3 ce1 (pipelined mode) d out q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a3y11) q(a1) (flow-through mode) t hzc t cdf t oe t lzoe
? as7c3128pfs32/36a 6/8/00 alliance semiconductor 7 timing waveform of write cycle note: ? = xor when mode = high/no connect; ? = add when mode = low. refer to burst sequence table. t cyc t cl t ss t sh t ss t sh t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address we ce0 , ce2 adv oe data in t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d]
? 8 alliance semiconductor 6/8/00 as7c3128pfs32/36a timing waveform of read/write cycle note: ? = xor when mode = high/no connect; ? = add when mode = low. refer to burst sequence table. t ch t cyc t cl t ss t sh t as t ah t ws t wh t advs t ds t dh t oh clk adsp address we ce0 , ce2 adv oe d in d out t lzc t advh t lzoe t oe t cd q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe (pipeline mode) d out q(a1) q(a3y01) q(a3) q(a3y10) (flow-through mode) t cdf
? as7c3128pfs32/36a 6/8/00 alliance semiconductor 9 notes ac test conditions as7c3128pfs32/36a ordering information as7c3128k32p and as7c3128pfs32/36a part numbering system ntd is a trademark of integrated device technology, inc. pentium is a trademark of intel corporation. package functionality 166 mhz 150 mhz 133 mhz 100 mhz tqfp pbsram as7c3128pfs32/36ap- 3.5tqc as7c3128pfs32/36a- 3.8tqc as7c3128pfs32/36a-4tqc as7c3128pfs32/36a-5tqc tqfp pbsram as7c3128pfs32/36a- 3.5tqc as7c3128pfs32/36a- 3.8tqc as7c3128pfs32/36a-4tqc as7c3128pfs32/36a-5tqc as7c 3 128k36 p Cxx xx c sram prefix operating voltage part number, organization timing ntd=ntd timing p=pbsram access time (ns) package: tq = tqfp commercial temperature, 0c to 70 c 1 this parameter is guaranteed but not tested. 2 for test conditions, see ac test conditions , figures a, b, c. 3 this parameter is sampled and not 100% tested. 4 this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk. all other synchronous inputs must meet the setup and hold times with sta ble logic levels for all rising edges of clk when chip is enabled. 5 typical values measured at 3.3v, 25c and 10 ns cycle time. 6i cc given with no output loading. i cc increases with faster cycle times and greater output loading. 7 transitions are measured 500 mv from steady state voltage. output loading specified with c l = 5 pf as in figure c. 8t hzoe is less than t lzoe ; and t hzc is less than t lzc at any given temperature and voltage. 9t hzcn is ano load parameter to indicate exactly when sram outputs have stopped driving. 351 w 5 pf* 317 w d out gnd +3.3v figure c: output load(b) *including scope and jig capacitance z 0 =50 w d out 50 w v l =1.5v figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v ? output load: see figure b, except for t lzc , t lzoe , t hzoe , t hzc see figure c. ? input pulse level: gnd to 3v. see figure a. ? input rise and fall time (measured at 0.3v and 2.7v): 2 ns. see figure a. ? input and output timing reference levels: 1.5v.
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